The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of the IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed.
For example, as the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design have resulted in the development of multilayer (or three dimensional) integrated devices. The multilayer devices may include a plurality of interlayer dielectric layers (ILDs) each including one or more conductive layers which are aligned and connected with other conductive layers. However, as the scaling down continues, forming and aligning conductive layers has proved difficult. Accordingly, although existing multilayer devices and methods of fabricating multilayer devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.